A SystemC cache simulator for a multiprocessor shared memory system
A SystemC cache simulator for a multiprocessor shared memory system
Author(s): Alfred MutangaSubject(s): Gender Studies
Published by: SciPress Ltd.
Keywords: Cache Coherency; Cache Simulator; Multiprocessor Architectures
Summary/Abstract: In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol.
Journal: International Letters of Social and Humanistic Sciences
- Issue Year: 2014
- Issue No: 02
- Page Range: 75-87
- Page Count: 13
- Language: English